1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for manufacturing interconnection plugs that can avoid the formation of recesses on plug surface.
2. Description of Related Art
Tungsten plug is now extensively used for interconnecting multiple layers in very large scale integration (VLSI). At present, how to control the formation of recesses in a tungsten etch-back operation is a major issue. To prevent short-circuiting current in the device caused by residual tungsten hanging onto the surface of a wafer, over-etching is often carried out during the tungsten etch-back operation. However, the longer the etching time is, the worse will be the phenomenon of recess formation on the surface of a tungsten plug. When the semiconductor demands a stack structure with a multiple of layers, the problem of recess formation will become worse. Recesses on the surface of the tungsten plug will lead either to a deterioration of the electrical properties of a semiconductor device or a low yield. Although the conventional chemical-mechanical polishing (CMP) method can redu!ce such recess formation, the machinery for carrying out the CMP operation are expensive and will increase the cost of production.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in the production of a plug according to a conventional method. First, as shown in FIG. 1A, a substrate 10 is provided. This substrate 10, for example, has a bottom metallic layer 12, which are designed for connecting with structures in other areas. Then, a chemical vapor deposition (CVD) method is used to form a dielectric layer 14 over the substrate. Next, conventional photolithographic and etching processes are used to pattern the dielectric layer 14 forming an opening 16 that exposes the bottom metallic layer 12.
Next, as shown in FIG. 1B, a glue layer 18 is formed over the bottom metallic layer 12 of the opening 16, the dielectric sidewalls of the opening 16, and the dielectric layer 14 itself. The glue layer serves to increase the adhesive strength of subsequently deposited plug material, as well as to act as an etching stop layer. The glue layer 18 can be a titanium nitride (TiN) composite layer, for example. The method of forming the glue layer 18 includes depositing a titanium nitride layer over the bottom metallic layer 12, the dielectric sidewalls of the opening 16 and the dielectric layer 14, then performing a chemical vapor deposition method to deposit a layer of TiN over dielectric layer 14 and dielectric sidewalls of the opening 16. In a subsequent step, a chemical vapor deposition method is used to deposit plug material 20 over the glue layer 18 above the dielectric layer 14 and the glue layer 18 above the opening 16. The plug material 20, for example, can be tungsten or aluminum.
Next, as shown in FIG. 1C, using an anisotropic dry etching method or a chemical-mechanical polishing (CMP) method, the plug material 20 is etched back removing the whole top layer of the plug material 20 and exposing the dielectric layer 14 so that a plug is formed with the remaining plug material. However, one of the defects in this conventional plug production method is the formation of recesses 22 on the plug surface.
Next, as shown in FIG. 1D, subsequent processes are performed. For example, a metallic layer 24 is deposited over the plug, and a stack structure that includes bottom metallic layer 12/plug/metallic layer 24 is formed. Because the plug surface has a recess, the metallic layer 24 also has a recess 26. When a multiple of these stacks are required in the semiconductor, the problem of recess formation will be amplified. Furthermore, in subsequent steps, when another layer of dielectric is deposited over this metallic layer 24, residual dielectric material that resides in the recess is difficult to remove, thereby leading to a deterioration of electrical properties or a lower yield.
In light of the foregoing, there is a need in the art to provide a better method for manufacturing interconnection plug.